Depending on the threshold voltage (Vt), FETs may be categorized as regular threshold voltage (RVT) devices, low threshold voltage (LVT) devices or super low threshold voltage (SLVT) devices. For example, to reach the leakage level of 0.1 nA/μm, 1 nA/μm and 10 nA/μm respectively, the Vt values for a RVT device, an LVT device and an SLVT device may be about 200 mV, 270 mV and 340 mV respectively. FETs may also be classified according to the various architectures, such as finFETs, horizontal nanosheet (hNS) FETs, vertical FETs, vertical nanosheet (vNS) FETs, etc.
The FETs based on channels formed of InGaAs (i.e., InGaAs channels) offer the possibility of high mobility, high injection velocity, and low gate capacitance.
Typically, the In fraction and the Ga fraction in the InGaAs channel add up to 1. Related art InGaAs channels typically utilize an In fraction of 53%. However, In0.53Ga0.47As devices also tend to have small bandgaps (approximately 75 meV, significantly less than 1.1 eV for Si). A consequence of this small bandgap is a large amount of Band-to-Band Tunneling (BTBT) leakage current. Because BTBT leakage is sensitive to the target threshold voltage (Vt) of the device, RVT devices may actually have more leakage than LVT and SLVT devices, compounding the difficulty of meeting their stricter off-current Ioff targets.
Given the leakage constraints on the RVT devices for mobile SOCs (about 0.1 nA/μm of the effective width of the transistor (Weff)), and also because BTBT leakage is exponentially sensitive to the supply voltage VDD and gate length Lg, BTBT imposes a strict upper bound on VDD (generally of about 0.7 V), and a lower bound on Lg (generally of about 12.5 nm). This makes In0.53Ga0.47As unsuitable for standard system on chip (SOC) applications, for example, for the central processing unit (CPU) cores of the SOC, since designs at present technology nodes generally require maximum operating voltages to be in the 0.9-1.4 V range, while even designs at the about 5 nm technology node will generally require maximum operating voltages to be at least in the 0.85-0.9 V range (a normal voltage (Vnom) of 0.65-0.7 V with a 200 mV overdrive for the maximum oscillation frequency (fmax)). It is noted that for the range of operating voltages in a SOC, the FETs must achieve a leakage current less than a specific value such that the total chip leakage power is less than or equal to a desired fraction of the overall chip power. Leakage current under overdrive conditions cannot be significantly higher (no more than 2-3×) than under nominal operating conditions.